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<p>Our client is an emerging leader in the arena of multi-million gate ICs for multimedia applications. With an emphasis on 3D graphics chips, their development team develops some of the largest and most complex digital ICs / SoC devices available in the market.
<p>This dynamic and motivated engineering team now seeks a physical design team leader / manager to help push their technology to a new level of efficiency. Joining a team of experienced back end designers, the successful candidate will be responsible for layout development, including scripting flows, and project management of cutting edge designs high speed, multi million gate ICs at small geometries (0.13u and below).
<p>You will be familiar with many or al of the following:
<li>Floorplanning
<li>Place and Route (Avanti, Cadence, Synopsys, etc)
<li>LVS / DRC checking
<li>Static timing
<li>Analogue design
<li>Formal verification
<p>This is a rare career opportunity combining challenge, responsibility, room for progression and the chance to significantly influence the success of a companys technology.
<p>Remuneration includes excellent basic (to 60k) as well as stock options and benefits.
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