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Our client is an international market leader that has been at the forefront of digital IC and software innovation for the last 15 years.
This Engineering team provides the expertise to translate CPU RTL and processor core macro cells into test chips and development chips. The team's responsibilities cover the whole digital IC implementation space from SoC RTL design and verification through the ASIC development flow to GDSII and post manufacturing silicon validation. The ideal candidate will be mainly working in small teams and interacting with customers, EDA vendors and other engineering groups based in the area.
In order to qualify for this position you will:
- Have experience of system architecture, validation and front end SoC implementation
- Have a good degree in an engineering or science related subject
- Have Knowledge of Unix, C, Assembler, Perl, Tcl (VHDL/Verilog would be a plus)
- Have experience in supervising/managing/coaching
- Have the ability to liaise with external groups and negotiate on technical specifications
- Track record of successful chip tape outs
- Have a good knowledge of system architecture, RTL design and validation
- Have experience of synthesis and netlist validation
- Have knowledge of place and route implementation EDA tools and transistor level sign off
- Have good analytical and communication skills
- Be proactive and able to "think out of the box"
- Have a good attitude towards new challenge
A working knowledge of a range of EDA implementation tools would be a plus
You will be responsible for:
- Architecting and designing SoC RTL
- Liasing with our board level design engineers in the development systems department
- Validating and verify the SoC designs through the use of leading edge validation techniques
- Contributing to peer reviews and quality inspections
- Developing new methodologies to improve the efficiency and quality of processor implementation
Please contact us for full details.
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