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Your responsibilities will include the full spectrum of SoC development activity from front-end RTL creation and validation through to synthesis, STA and potentially place and route with physical verification and final tape-out. Full chip implementation projects provide exposure to all stages of the design flow and require flexible, multi-disciplined engineers who are likely to be experts in particular elements of the flow but are also familiar with other tasks. You will have at least 5 years SoC design experience with specific experience in some of the following - RTL creation including familiarity with Verilog/VHDL simulation tools, and testbench design. Advanced verification tools such as SPECMAN Elite/ e programming language would be an advantage. Experienced at synthesis using Synopsys DC and PC. Experienced with PrimeTime STA. Familiarity with physical verification at 0.18um, 0.13um and preferably 90nm. Experience of JupiterXT / Astro hierarchical floorplan & layout tools would be an advantage. Experience of Physical Verification DRC, LVS (Calibre), Power Analysis with AstroRail. Remuneration includes one of the best benefits packages available in the industry. Please contact us as soon as possible to discuss your interest.
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